The present invention relates to semiconductor memory devices, and in particular, the invention relates to a multiplexed data transfer system and method for controlling the transfer of data from a memory array to the data outputs of an integrated circuit memory device, and for providing programmable latency control in the data transfer operation.
As microprocessors have become faster, a need has developed for speeding up memory usage. Various arrangements have been proposed for reducing access time for semiconductor memory devices, such as synchronous dynamic random access memory devices. One of the most common approaches for speeding up memory usage is through the use of pipelining arrangements. In pipelining arrangements, data that is read out of a memory is temporarily held in data registers interposed in the data path between the memory array and output buffers of the input/output circuits of the memory system until needed, allowing the memory to be accessed to read out other data. Many known pipelining arrangements require clocked storage elements in the address buffer, the column switch and in the data output path to maintain synchronization between the data and the system. The need for these clocked storage elements places a restriction on the clock frequency of the system clock.
A further consideration is that pipelining arrangements require internal clock pulses for controlling the sequencing of the data transfer operations. In many instances such internal timing signals are derived from the system clock, typically using counter circuits. The counter circuits divide the system clock pulses to produce a series of internal clock pulses having a predetermined relation to the clock pulse. However, the timing signals that are produced using a counter circuit have an inherent skew because the system clock pulses must ripple through several stages of the counter circuit in producing the internal clock pulses. Moreover, in producing a multi-phase internal clock signal using counter circuits, the output of the counter circuits must be sampled to detect a 1xe2x80x941 state followed by activation of the reset input of the counter circuit. This results in a time delay and further skews the output signal provided by the counter circuit based internal clock pulse generator. Other clock pulse generating circuits employ inverter circuits for producing sequenced clock pulses. However, the inverter circuits introduce delays that must be compensated for to avoid speed loss.
A synchronous dynamic random access memory employing wave pipelining methods is disclosed in an Article entitled xe2x80x9cA 150 MHz 8-Banks 256M Synchronous DRAM with Wave Pipelining Methodsxe2x80x9d by Hoi-Jun Yoo, et. al, which appeared in the 1995 IEEE International Solid State Circuits Conference. Digest of Technical Papers, pages 250, 251 and 374, Feb. 17, 1995. The memory includes steering circuitry in the data path which transfers data to and from the data output registers according to external latency programming. However, this arrangement requires separate clock signals for data reception from the pipelining path and for data transfer to the output driver.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a multiplexed data transfer system and method for controlling the transfer of data retrieved from a memory array to data outputs of a semiconductor memory and for providing programmable latency control in the data transfer operation.
The present invention provides a multiplexing arrangement for controlling the transfer of data retrieved from a memory array of a semiconductor memory to data outputs of the semiconductor memory and for providing programmable latency control in the data transfer operation. The multiplexing arrangement comprises a data output register which includes a plurality of data storage circuits for storing data that is retrieved from the memory array. A multiplexing circuit is responsive to timing signals produced by a timing signal generator to load data that is retrieved from the memory array into the data storage circuits of the data output register. The timing signals are also used to read the data from the data storage circuits of the data output register for passing the data from the data output register to the data outputs of the semiconductor memory. The multiplexing circuit responds to the timing signals and to a latency select signal to load the data into the data storage circuits in a sequence that establishes a known delay between the time that the data is retrieved from the memory array, and stored in the data output register, and the time that data stored in the data output register is passed to the data outputs. The delay allows data to be held in the data output register when the data is available and to be passed to the data outputs of the semiconductor memory when desired.
In accordance with another aspect of the invention, there is provided a multi-phase timing signal generator which is characterized by fast speed. The timing signal generator comprises a multi-stage shift register connected for operation as a recirculating shift register. The shift register stages store a predetermined bit pattern and a drive circuit, responsive to system clock pulses, advances the bit pattern through the shift register. An output circuit logically combines the signals provided on signal outputs of the shift register stages as the bit pattern is advanced through the shift register to produce a sequence of timing signals. In one embodiment, the drive circuit comprises a pair of two-stage drive shift registers storing complementary bits which change in state in response to system clock pulses, for producing complementary bit pattern advance signals for the multi-stage shift register. This arrangement produces complementary drive signals without the need for inverters, and thus eliminates the delay introduced by inverters.
The timing signal generator is particularly useful for latency control in the transfer of data retrieved from a memory array of a semiconductor memory to data outputs of the semiconductor memory. In such application, the timing signal generator includes a latency control circuit which delays the response of the timing signal generator by one system clock pulse to provide a clock latency of one for the data transfer arrangement.